IISWC-2008 September 14-16, 2008 Seattle, WA, USA |
PROGRAM
September 14 (Sunday) |
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8:00 - 12:00 pm Tutorial I (20 minute coffee break at 9:50 am) 1:30 - 5:30 pm Tutorial II and III (20 minute coffee break at 3:20 pm) |
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September 15 (Monday) |
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8:00 - 8:30am
Breakfast
11:45 - 1:15pm Lunch
6:00 pm - IISWC excursion: Seattle underground tour event |
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September 16 (Tuesday) |
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8:00 - 8:45am
Breakfast 8:45 - 9:45am Keynote II: We have it easy, but do we have it right? 9:45 -10:15am Break 10:15 -11:45am Session 4: Commercial Workloads 11:45 - 1:15pm Lunch 1:15 - 2:15pm Session 5: Architecture Issues 2:15 - 2:45pm Break 2:45 - 4:15pm Session 6: Workload Fidelity |
Day 1 - Sunday, September 14, 2008
Using the Pin Instrumentation Framework for Workload Characterization, Aamer Jaleel, Cristiano Pereira (Intel Corporation)
Transactional Memory for C/C++: Design, Implementation and Performance, Adam Welc, Yang Ni, and Ali-Reza Adl-Tabatabai (Intel Corporation)
Fast Simulation without Bogus Results, Tom Conte, Paul Bryan (Georgia Institute of Technology)
Day 2 - Monday, September 15, 2008
8:00 - 8:30am Breakfast
8:30 - 8:45am Welcome
8:45 - 9:45am
Keynote I:
Wild Speculation on Consumer
Workloads in 2010-2020
(Session chair:
Tom Conte, Georgia Tech)
slide
Speaker: Tim
Sweeney, Epic Games Inc.
9:45 -10:15am Break
10:15 -11:45am
Session 1: Multicore Systems
(Session chair: Brad Waters, Microsoft)
Energy-Aware Application Scheduling on a Heterogeneous Multi-core System, Jian Chen (UT-Austin) Lizy K. John (UT-Austin) paper slide
Parallelization and Characterization of SIFT on Multi-Core Systems, Hao Feng (Intel China Research Center) Eric Li (Intel China Research Center) Yurong Chen (Intel China Research Center) Yimin Zhang (Intel China Research Center) paper slide
Implications of Cache Asymmetry on Server Consolidation
Performance, Padma Apparao (Intel Corporation) Ravi Iyer (Intel
Corporation) Don Newell (Intel Corporation)
paper
slide
11:45 -1:15pm Lunch
1:15 - 2.45pm
Session 2: Benchmarks and
Runtimes for Thread Parallelism
(Session chair: Thomas Wenisch, U. of Michigan)
STAMP: Stanford Transactional Applications for Multi-Processing, Chi Cao Minh (Stanford University) JaeWoong Chung (Stanford University) Christos Kozyrakis (Stanford University) Kunle Olukotun (Stanford University) paper slide
PARSEC vs. SPLASH-2: A Quantitative Comparison of Two Multithreaded Benchmark Suites on Chip-Multiprocessors, Christian Bienia (Princeton University) Sanjeev Kumar (Intel Corporation) Kai Li (Princeton University) paper slide
Characterizing and Improving the Performance of The Intel Threading Building Blocks, Gilberto Contreras (Princeton University) Margaret Martonosi (Princeton University) paper slide
2:45 - 3:15pm Break
3:15 - 4:45pm
Session 3: Emerging Workloads
(Session chair: Engin Ipek, Microsoft Research)
Whiteboards that Compute: A Workload Analysis, Ryan Dixon (University of California, Santa Barbara) Timothy Sherwood (University of California, Santa Barbara) paper slide
A Workload for Evaluating Deep Packet Inspection Architectures, Michela Becchi (Washington University) Mark Franklin (Washington University) Patrick Crowley (Washington University) paper slide
Empirical Examination of A Collaborative Web Application,
Christopher Stewart (Univ of Rochester) Matthew Leventi (Univ of Rochester) Kai Shen (Univ of Rochester)
paper
slide
6:00 pm - IISWC Excursion: Seattle Underground Tour Event
Day 3 - Tuesday, September 16, 2008
8:00 - 8:45am
Breakfast
8:45 - 9:45am
Keynote II:
We have it easy, but do we
have it right?
(Session chair: Steve Reinhardt, AMD)
slide
Speaker: Amer Diwan, University of Colorado at Boulder
9:45 -10:15am Break
10:15 -11:45am
Session 4: Commercial Workloads
(Session chair: Aamer Jaleel, Intel)
11:45 - 1:15pm Lunch
1:15 - 2:15pm
Session 5: Architecture Issues
(Session chair: Priya Nagpurkar, IBM Research)
2:15 - 2:45pm
Break
2:45 - 4:15pm
Session 6: Workload Fidelity
(Session chair: Leslie Barnes, AMD)
Keynotes
Keynote I: Wild Speculation on Consumer Workloads in 2010-2020
Speaker: Tim Sweeney, Founder & Technical Director, Epic Games Inc.
Abstract:
Games are among the most performance-intensive consumer applications, and often lead the way in bringing research technologies into practice. This occasionally leads to non-evolutionary leaps in performance and workload characteristics, such as the 1000-fold increase in 3D throughput enabled by consumer graphics accelerators beginning in 1998.
The speaker will argue that another revolution in consumer computing performance is on the horizon, driven by large-scale multi-core CPUs with vector-processing extensions inspired by today's graphics processors (GPUs). He will present a view of the key problems and solutions facing consumer software developers in 2010-2020, and speculate on the shape and scale of workloads in that timeframe. The essential questions to cover are: What portions of an application can scale effectively to many cores and vector processors? How and when can concurrency research bring techniques like functional programming, software transactional memory, and vectorization into mainstream practice?
Speaker's bio:
Tim Sweeney founded Epic Games in 1991 and wrote two of the company's early shareware games, ZZT and Jill of the Jungle. From 1995 to 1998, he wrote the first Unreal Engine, which powered a number of hit games including Unreal Tournament, Splinter Cell, Harry Potter, and Deus Ex. Today, Sweeney is overseeing the development of its latest Unreal Engine 3 technology while working on early R&D efforts for the following generation, aimed at large-scale multi-core processors.
Keynote II: We have it easy, but do we have it right?
Speaker: Amer Diwan, Associate Professor, University of Colorado at Boulder
Abstract:
To evaluate an innovation in computer systems, performance analysts measure execution time or other metrics using one or more standard workloads. The performance analyst may carefully minimize the amount of measurement instrumentation, control the environment in which measurement takes place, and repeat each measurement multiple times. Finally, the performance analyst may use statistical techniques to characterize the data.
Unfortunately, even with such a responsible approach, the collected data may be misleading due to measurement bias and observer effect. Measurement bias occurs when the experimental setup inadvertently favors a particular outcome.
Observer effect occurs if data collection alters the behavior of the system being measured. This talk demonstrates that observer effect and measurement bias are (i) large enough to mislead performance analysts; and (ii) common enough that they cannot be ignored.
While these phenomenon are well known to the natural and social sciences this talk will demonstrate that research in computer systems typically does not take adequate measures to guard against measurement bias and observer effect.
Speaker's Bio:
Amer Diwan is an associate professor at the University of Colorado at Boulder. Before joining the University of Colorado, he was at the University of Massachusetts at Amherst for his PhD and at Stanford University for his postdoc. His research interests include tools and techniques for understanding program performance, programmer productivity tools, program analysis, memory management, and compiler optimizations.