October 4-6, 2015

 Atlanta, Georgia, USA


Tutorial I: Contech: Modeling and Analyzing Parallel Programs with Task Graphs (9am to 12:30pm, half day)

In this tutorial, we will present Contech, a comprehensive parallel program instrumentation and analysis framework that supports a diversity of languages, runtimes, and architectures. We will introduce the task graph representation that Contech uses and demonstrate how the framework efficiently generates task graphs from parallel programs. Through hands-on exercises, we will rapidly prototype a variety of analyses. There will also be time to cover the instrumentation's design as well as how it can be extended to cover new functionality and scenarios. The tutorial will use both x86 and ARM platforms, and will assume a working knowledge of C/C++.

More information can be found here: http://tinker.cc.gatech.edu/contech_iiswc2015

Tutorial II: Wind River® Simics and Intel® SAE: Dynamic Binary Instrumentation of OS Kernel, Driver and BIOS (9am to 12:30pm, half day)

The tutorial covers the use of Intel® SAE tools (called ztools) for conducting different types of architectural and program analysis' studies, such as cache modeling, instruction usage characterization and new instruction emulation. The tutorial also covers how users can write their own new tools using Intel® SAE generic APIs. If you used Pin or written a PinTool, you will find Intel SAE ztools very useful. Beyond Pin-like features, it performs distributed node-to-node multi-system simulation, useful for analysis of enterprise-scale workloads, such as CloudSuite, Hadoop, Memcached etc.

More information can be found here: https://sites.google.com/site/intelsae/

Tutorial III: Open-Source Benchmarks for Online Data-Intensive Services (1:30pm to 5pm, half day)

When users search Google or browse titles on Netflix, they expect to find what they seek with fast response times. Instead of accessing a few, well-defined data records for each query, OLDI services scan large non-indexed data sets. Online systems such as these can be made up of many components in the cloud, with varying access times that can impact performance and answer quality. In our tutorial, we explain how to use open-source components such as OpenEphyra and Lucene/Solr as benchmarks for these online, data-intensive services.

More information can be found here: http://web.cse.ohio-state.edu/~kelleyj/ubora/tutorial.html

Tutorial IV: Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory-NoC Simulation (1:30pm to 5pm, half day)

In this tutorial, we discuss Sigil; a workload profiling toolset that allows architects to explore and investigate sources of performance bottlenecks in current and future systems. Sigil captures platform-independent behavior from workloads which can be used to assist HW/SW partitioning problems and to assist trace-based simulation of multi-threaded workloads on CMPs. This tutorial also presents SynchroTrace, a simulation framework built on top of Sigil to perform trace-based simulation.

More information can be found here: http://ece.drexel.edu/faculty/taskin/wiki/vlsilab/index.php/Tutorials:SynchroTrace_Sigil_2015