September 30 - October 2, 2018

 Raleigh, North Carolina, USA

On the Performance Cost of Secure Execution Environment

Yan Solihin
Charles N. Millican Chair Professor of Computer Science at University of Central Florida
Director for Cybersecurity and Privacy Cluster
IEEE Fellow

There is an increasing demand for the processor architecture to provide secure execution environment in various compute platforms including the cloud and Internet of Things (IoT) devices. Current secure execution environment suffers from two serious drawbacks. First, the threat model is incomplete, as evident in recent side channel attacks, leaving the system vulnerable to attacks. Furthermore, despite intensive research, providing secure execution environment for current threats is expensive, let alone for protecting against new threats. In this talk, I will discuss performance overheads of providing secure execution environment, and argue that it is one of the most important emerging hot workloads.


Yan Solihin is a Charles N. Millican Chair Professor of Computer Science at University of Central Florida, Director for Cybersecurity and Privacy Cluster, and an IEEE Fellow. He obtained his Ph.D. degree in computer science from the University of Illinois at Urbana-Champaign in 2002. He is a recipient of 2010 and 2005 IBM Faculty Partnership Award, 2004 NSF Faculty Early Career Award, and 1997 AT&T Leadership Award. He is well known for pioneering cache sharing fairness and Quality of Service (QoS), efficient counter mode memory encryption, and Bonsai Merkle Tree, which have significantly influenced Intel Cache Allocation Technology and Secure Guard eXtension (SGX) design. In 2017, he received IEEE Fellow “for contributions to shared cache hierarchies and secure processors”. He is listed in the HPCA Hall of Fame and ISCA Hall of Fame.

From 2015-2018, he was a Program Director at the Division of Computer and Network Systems (CNS) at the National Science Foundation. His responsibilities include managing the Secure and Trustworthy Cyberspace (SaTC), Computer Systems Research (CSR), and Scalability and Parallelism in the eXtreme (SPX). He co- founded the NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR) program.

His research interests include computer architecture and systems for security. He has authored more than 90 journal/conference papers, 40 US patents, 2 graduate textbooks, and delivered 70+ invited talks/seminars, including several keynote presentations and multi-day tutorials. His research has received MICRO Best Paper Runner-up Award (2017), IEEE Micro Top Picks (2011), and several Best Paper nominations/finalists.