September 30 - October 2, 2018
Raleigh, North Carolina, USA
Computer architects have made great strides in the last decade on improving performance and energy efficiency of "regular" parallel computations, i.e., those that are embarrassingly parallel, have simple memory access patterns, have simple or predictable control flow, and whose behavior is independent of input values. However, irregular computations, i.e., those that violate one or more of the above properties of regular computations, remain an enormous challenge. This in part due to the diversity of the workload space, and in part due to our desire to maintain our hard-earned efficiency gains on regular computations. I will highlight application examples of the key architectural challenges in irregular computations, and discuss some "lightweight" architectural features that we are driving to help address those challenges.
Chris Hughes is a Principal Engineer and leads a team within Intel Labs, focusing on workload-driven
processor architecture research, for highly parallel workloads such as high-performance computing,
machine learning, and big data analytics.
Chris joined Intel in 2003, after completing his Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign. He led the teams that defined the AVX2/AVX-512 gather and scatter instructions, and conflict detection instructions (i.e., AVX-512CD). In addition to his work on SIMD ISA, he has led projects on cache optimizations for many-core architectures, core-to-core communication and synchronization, and transactional memory. He was on the team that won Intel's highest technical award, for demonstrating the value of many-core architectures in the server space, leading to the Intel Xeon Phi product line. In addition to work on computer architecture, he has published work on developing, characterizing, and optimizing parallel algorithms, including on molecular dynamics, speech recognition, and articulated body tracking.